DK-NIOS-2C35N【PDF 14/64 页】NIOS II KIT W/CYCLONE II EP2C35N

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Board Components

Table 2–1. Nios Development Board, Cyclone II Edition Components & Interfaces (Continued)

Board Designation

Memory

U74

U5, LED7

U63

Connections & Interfaces

U4, RJ1

J19

Name

SSRAM memory

Flash memory

DDR SDRAM memory

Ethernet MAC/PHY

Serial connector

Description

2 Mbytes of synchronous SRAM.

16 Mbytes of nonvolatile memory for use by both the

FPGA and the configuration controller. LED7 lights

whenever the flash chip-enable is asserted.

32 Mbytes of DDR SDRAM.

10/100 Ethernet MAC/PHY chip connected to an RJ-

45 Ethernet connector.

RS-232 serial connector with 5 V-tolerant buffers.

Supports all RS-232 signals.

PROTO1 (J11, J12, J13) Expansion prototype

connector

PROTO2 (J15, J16, J17) Expansion prototype

connector

Expansion headers connecting to 41 I/O pins on the

FPGA. Supplies 3.3V and 5.0V for use by a daughter

card.

Expansion headers connecting to 41 I/O pins on the

FPGA. Supplies 3.3V and 5.0V for use by a daughter

card.

CON3

JH1, JH2

J25

TP1 – TP8

J24

J5

J27

CompactFlash connector

PMC connector

Mictor connector

Test Points

JTAG connector

JTAG connector

EPCS configuration header

CompactFlash connector for memory expansion.

Expansion connector for a PCI mezzanine card.

Mictor connector providing access to 27 I/O pins on

the FPGA. Allows debugging Nios II systems using a

First Silicon Solutions (FS2) debug probe.

Test points providing access to eight FPGA I/O pins.

JTAG connection to the FPGA allowing hardware

configuration using the

Quartus ? II software and software debug using the

Nios II IDE.

JTAG connection to the MAX ? configuration

controller.

Connects to the EPCS serial configuration device for

in-system programming.

Configuration & Reset

U3

MAX Configuration controller Altera MAX EPM7256AE device used to configure

the FPGA from flash memory.

U69

SW8

Serial configuration device

CPU Reset button

Altera EPCS64 low-cost serial configuration device to

configure the FPGA.

Push-button switch to reboot the Nios II processor

configured in the FPGA.

2–2 Reference Manual

Nios Development Board Cyclone II Edition

Altera Corporation

May 2007

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